Principal design engineer
KarnatakaMulya Technologies
...System Verilog/Verilog and scripting (Python/Perl). Experience with block-level and full-chip design at advanced nodes (≤ 16nm). Silicon bring-up and post-silicon debug experience. Familiarity with industry standard simulation, debug, quality checking and synthesis tools Synopsys/Cadence tools and UVM-based design [...]
Category Education, Training, & Library
21 days ago in Labor24