Design verification engineer - system verilog
BangaloreRecruitment Firm
...Use automation scripts (Python, Perl, Makefile) and EDA tools (e.g., Synopsys VCS, Cadence Xcelium) for regression testing.Required Skills and Qualifications :- Methodologies : Strong knowledge of constrained-random verification, SystemVerilog, and UVM.- Technical Knowledge : Proficient in RTL simulation, debugging techniques, [...]
Category Fashion & Arts
3 days ago in Hirist