Senior design verification engineer - system verilog/uvm
MetrosVarite
...design and architecture specifications- Build scalable and reusable SystemVerilog/UVM-based testbenches- Perform block-level and SoC-level functional verification- Verify high-speed interfaces such as PCIe- Validate memory subsystems including DDR/LPDDR- Work on processor-based systems with knowledge of x86 architecture- [...]
Category IT & Telecommunications
15 hours ago in Hirist