Design verification engineer - system verilog
Bangalore/Hyderabad/Noida/Ahmedabad/PuneSemi leaf
...end-to-end verification flows- Experience developing and maintaining block-level, IP-level, or SoC-level testbenchesTechnical Skills :- Proficient in SystemVerilog and UVM- Hands-on experience with testbench architecture, sequences, scoreboards, and monitors- Experience working with complex verification environments using [...]
Category IT & Telecommunications
5 days ago in Hirist