Design verification engineer - system verilog
Bangalore/Hyderabad/Noida/Ahmedabad/PuneSemi leaf
...disciplinesLocation : : 5-12 yearsSkills : SOC/ IP/Subsystem Verification :Job Summary :We are seeking a passionate and experienced Design Verification Engineer with strong hands-on expertise in System Verilog and UVM methodology.The ideal candidate will have a solid understanding of IP- and SoC-level [...]
Category IT & Telecommunications
17 days ago in Hirist