Formal verification engineer
BengaluruAccenture
...languages: all sign-off simulators, waveform debugging tools like Simvision / Verdi • Fluent in verification language such as UVM/OVM/RVM/System Verilog, Vera, Verilog • Experience in writing test-plans and creating directed and random test cases • Strong scripting skills in Perl, Python, shell etc. • Strong [...]
Job Type: Full-time
Category IT & Telecommunications