Tessolve - lead design verification engineer - system verilog
Bangalore/Chennai/HyderabadTessolve Semiconductor
...teams across geographies- Mentor junior verification engineers and contribute to best practicesTechnical Skills : Verification Languages & Methodologies : - SystemVerilog, UVMProtocols & Interfaces : - AHB, AXI, APB- GPIO, SPI, I2C, UART- PCIe, USB, MIPI, DDR, UPF (any one or more)Verification Tools : - Synopsys VCS or Cadence [...]
Category IT & Telecommunications
30 days ago in Hirist