Tessolve - senior verification engineer - soc/system verilog
BangaloreTessolve Semiconductor
...Lead the development and maintenance of SystemVerilog/UVM-based verification environments- Drive coverage closure, including functional and code coverage, and ensure verification completeness- Perform subsystem-level and SoC-level verification, including integration and corner-case testing- Verify high-speed protocols and [...]
Category IT & Telecommunications
21 days ago in Hirist