Rtl design engineer - system verilog
BangaloreSemi leaf
...Debug RTL vs synthesis mismatches and functional issues- Collaborate closely with Design Verification (DV) teams to resolve bugs efficiently- Develop solid synthesis-friendly RTL with correct constraint intent at block/top level- Support timing closure in collaboration with PD and STA teams- Maintain clear and up-to-date RTL [...]
Category IT & Telecommunications
5 hours ago in Hirist