Principal electrical engineer (dv)
Karnataka
...to understand the verification requirements and participate in UVM or SystemVerilog testbench development.Required Experience and Skills::8+ years (BSEE), 6+ years (MSEE), or 3+ years (PhD) of relevant industry experience:Expertise in developing testbenches using System Verilog and UVM:Experience using directed and [...]
Category Electronics
3 days ago in TipTopJob